刘波简介

发布者:方文凯发布时间:2020-05-09浏览次数:5712

个 人 简 历

  

基本资料

 ·姓名: 刘波

 ·性别: 男

 ·出生年月: 1984.04

 ·民族: 汉

 ·职称: 讲师

 ·学历: 博士

 ·职务:

 ·联系电话: 13770715769

·E- mail liubo_cnasic@seu.edu.cn

 

个人简历


刘波,东南大学电子科学与工程学院,讲师,硕导,主要研究方向为低功耗智能计算架构与电路设计。先后负责国家自然科学基金1项、国家科技重大专项1项,承担企业技术研发合作项目1项;并参与多项国家自然科学基金、863重点项目等国家级科研课题。作为技术骨干参与十一五、十二五863高能效计算架构与电路设计相关科研攻关项目,负责其中部分关键技术的研发,项目成果获2014年教育部技术发明一等奖、2015年国家技术发明二等奖。近5年,发表20余篇国际知名期刊和会议论文,包括IEEE TCAS-I (电路与系统Top期刊)TCAS-IITVLSITMMicroelectronics JournalSCI期刊,以及DATE (EDATop会议之一)ISCASGLSVLSIFPTDSP国际会议论文,申请发明专利20余项,国际PCT专利4项,其中13项已获授权。此外,作为指导老师获得多个设计竞赛奖项,包括:2017全国大学生集成电路创新创业大赛全国总决赛优秀指导教师称号,2017全国大学生FPGA创新设计邀请赛企业特别奖,2018中国研究生创新实践系列大赛“华为杯”全国总决赛二等奖,2018年第十三届中国研究生电子设计竞赛团队二等奖,2018年全国大学生FPGA创新设计邀请赛一等奖,2019年全国集成电路创新创业大赛全国总决赛二等奖,2020全国集成电路创新创业大赛全国总决赛一等奖,2020华为杯创芯大赛全国总决赛二等奖等。此外,还获得首届中国电子信息行业创新创业大赛总决赛优秀奖2020),首届集成电路产业设计大赛总决赛二等奖(2020)。201812届全国计算机体系结构学术年会作分论坛特邀报告“精度可控近似计算电路设计”。指导学生在IEEE SiPS2017FPT2019NANOARCH2019ISSCC2020 SRP国际权威会议上发表论文,并获11th IEEECyberC Honorable Student Paper Award。教学方面,担任本科课程 “VLSI系统导论”(自2014年起)、研究生课程“数字集成电路设计”和“数字集成电路EDA技术”(自2015年起)的教学工作;获东南大学中泰国立奖教金(2019年)。担任IEEE Transactions on Circuits and Systems II: Express Briefs (IF:2.814)ACM Computing Surveys (IF:7.99)Elsevier Neurocomputing (IF:4.438)IEEE Open Journal of Circuits and SystemsElsevier Microelectronics Journal (IF:1.405)Elsevier Computers and Electrical Engineering (IF:2.663)IEEE Access (IF:3.745)CCF Transactions on High Performance Computing,浙江大学学报(工学版)等国内外期刊审稿人,以及IEEE NANOARCH2019等国际会议分会主席


【 研究方向


高能效智能计算架构与电路,低功耗数字集成电路,可重构近似计算,及相关VLSI设计。


研究成果


期刊论文: 

  1. B. Liu, H. Cai, Z. Wang, Y. Sun, Z. Shen, W. Zhu, Y. Li, Y. Gong, W. Ge, J. Yang, L. Shi, "A 22nm, 10.8 μW/15.1 μW Dual Computing Modes High Power-Performance-Area Efficiency Domained Background Noise Aware Keyword- Spotting Processor," IEEE Transactions on Circuits and Systems I: Regular Papers (IEEE TCAS-I), vol. 67, no. 12, pp. 4733-4746, 2020.

  2. H. Cai, M. Han, Y. Zhou, B. Liu and L. A. de Barros Naviner, "Triple Sensing Current Margin for Maintainable MRAM Yield at Sub-100% Tunnel Magnetoresistance Ratio," IEEE Transactions on Magnetics, Early Access.

  3. H. Cai, M. Liu, Y. Zhou, B. Liu, L.A.B. Naviner,"CSME: A novel cycle-sensing margin enhancement scheme for high yield STT-MRAM, "Microelectronics Reliability,Vol. 114,2020.

  4. W. Ge, S. Hu, J. Huang, B. Liu, M. Zhu, “FPGA implementation of a challenge pre-processing structure arbiter PUF designed for machine learning attack resistance”, IEICE Electronic Express, vol. 17, no. 2, 2020.

  5. Y. Zhou, H. Cai, B. Liu, W. Zhao and J. Yang, "MTJ-LRB: Proposal of MTJ-based Loop Replica Bitline as MRAM Device-Circuit Interaction for PVT-Robust Sensing", IEEE Transactions on Circuits and Systems II: Express Briefs (IEEE TCAS-II), vol. 67, no. 12, pp. 3352-3356, 2020.

  6. B. Liu, Z. Wang, S. Guo, H. Yu, Y. Gong, J. Yang, L. Shi, “An energy-efficient voice activity detector using deep neural networks and approximate computing”, Microelectronics Journal, vol. 87, pp. 12-21, 2019.

  7. Y. Gong, B. Liu(*通信作者), W. Ge, L. Shi, ARA: Cross-Layer approximate computing framework based reconfigurable architecture for CNNs, Microelectronics Journal, vol. 87, pp. 33-44, 2019.

  8. B. Liu, Z. Wang, W. Zhu, Y. Sun, Z. Shen, L. Huang, Y. Li, Y Gong, W Ge, “An Ultra-Low Power Always-On Keyword Spotting Accelerator Using Quantized Convolutional Neural Network and Voltage-Domain Analog Switching Network-Based Approximate Computing”, IEEE Access, vol. 7, pp. 186456-186469, 2019.

  9. B. Liu, Z. Wang, H. Fan, J. Yang, B. Liu, W. Zhu, L. Huang, Y. Gong, W. Ge, L. Shi,“EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing,” IEEE Access, vol. 7, pp. 82453-82465, 2019.

  10. B. Liu, H. Qin, Y. Gong, W. Ge, M. Xia, L. Shi, “EERA-ASR: An Energy-Efficient Reconfigurable Architecture for Automatic Speech Recognition With Hybrid DNN and Approximate Computing”, IEEE Access, vol. 6, pp. 52227-52237, 2018.

  11. Z.Wang, M. Xia, B. Liu(*通信作者), X. Ruan, Y. Gong, J. Yang, W. Ge and J. Yang, EERA-DNN: An energy-efficient reconfigurable architecture for DNNs with hybrid bit-width and logarithmic multiplier”, IEICE Electronics Express, vol. 15, no. 8, 2018.

  12. P. Cao, B. Liu, J. Yang, J. J. Yang, M. Zhang, L. Shi, “Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications”, IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI), vol. 2, pp. 2321-2331, 2017.

  13. B. Liu, W. Dong, T. Xu, Y. Gong, W. Ge, J. Yang and L. Shi, “E-ERA: An Energy-Efficient Reconfigurable Architecture for RNNs Using Dynamically Adaptive Approximate Computing”, IEICE Electronics Express, vol. 14, no. 15, 2017.

  14. C. Wang, P. Cao, B. Liu and J. Yang, “Coarse-grained Reconfigurable Architecture with Hierarchical Context Cache Structure and Management Approach”, IEICE Electronics Express, vol. 14, no. 6, 2017.

  15. B. Liu, X. Wang, D. Zhang and W. Ge, “Data Memory Structure and Management Strategy of Reconfigurable System for Radar”, Journal of Shanghai Jiaotong University, vol. 51, no. 5, pp. 628-635, 2017. (inChinese)

  16. B. Liu, C. Ji, W. Zhu and C. Mei, “Optimization of reconfigurable processor based on dynamic configuration context compression”, Journal of Southeast University (Natural Science Edition), vol. 45, no. 5, pp. 822-827, 2015. (inChinese)

  17. B. Liu, P. Cao, M. Zhu, J. Yang, L. Liu, S. Wei and L. Shi, “Reconfiguration process optimization of dynamically coarse grain reconfigurable architecture for multimedia applications”, IEICE Transactions on Information and Systems, vol. E95-D, no. 7, pp. 1858-1871, 2012.



会议论文:

  1. B. Liu, Z. Shen, L. Huang, Y. Gong, Z. Zhang and H. Cai, “A 1D-CRNN Inspired Reconfigurable Processor for Noise-robust Low-power Keywords Recognition,” Accepted by DATE 2021. (Acceptance rate: 24%)

  2. B. Liu, H. Cai, Y. Gong, W. Zhu, Y. Li, W. Ge, Z. Wang, “Binarized Weight Neural-network Inspired Ultra-low Power Speech Recognition Processor with Time-domain based Digital-analog Mixed Approximate Computing”, IEEE International Symposium on Circuits and Systems (IEEE ISCAS), pp. 1-5, 2020.

  3. B. Liu, Y. Sun, H. Cai, Z. Shen, Y. Gong, L. Huang and Z. Wang, “An Ultra-low Power Keyword-Spotting Accelerator Using Circuit-Architecture-System Co-design and Self-adaptive Approximate Computing Based BWN”, ACM 30th Great Lakes Symposium on VLSI (GLSVLSI), pp. 193-198, 2020.

  4. B. Liu, Y. Li, L. Huang, H. Cai, W. Zhu, S. Guo, Y. Gong, “A Background Noise Self-adaptive VAD Using SNR Prediction Based Precision Dynamic Reconfigurable Approximate Computing”, ACM 30th Great Lakes Symposium on VLSI (GLSVLSI), pp. 271-275,2020.

  5. Y. Li, X. Ding, H. Yang, X. Zhang, Y. Gong, B. Liu (*通信作者), “A 681 GOPS/W~3.59 TOPS/W CNN Accelerator Based on Novel Data Flow Scheduling Scheme,” IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, 2020.

  6. L. Huang, Z. Zhang, H. Yang, Y. Sun, Y. Gong, Wei Ge, B. Liu (*通信作者), “Low Power Keyword Recognition Accelerator based on Approximate Calculation of Deep-Shift Neural Network,” IEEE 15th International Conference on Solid-State and Integrated Circuit Technology, 2020.

  7. Y. Gong, B. Liu (*通信作者), W. Ge, L. Shi, “RNA: Reconfigurable LSTM Accelerator with Near Data Approximate Processing,” IEEE 18thInternational Conference on Field-Programmable Technology (IEEE FPT), pp. 311-314, 2019.

  8. B. Liu, Y. Sun and B. Liu, “.Translational Bit-by-Bit Multi-bit Quantization for CRNN on Keyword Spotting”, International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, pp. 444-451, 2019.

  9. W. Ge, J. Huang, B. Liu, M. Zhu, Y. Cao, “A Deep Learning Modeling Attack Method for MISR-APUF Protection Structures”, IEEE Asia Pacific Conference on Circuits and Systems (IEEE APCCAS), pp. 398-402, 2018.

  10. B. Liu, S. Guo, H. Qin, Y. Gong, J. Yang, W. Ge, J. Yang, “An Energy-efficient Reconfigurable Hybrid DNN Architecture for Speech Recognition with Approximate Computing”, IEEE 23rd International Conference on Digital Signal Processing (IEEE DSP), pp. 1-5, 2018.

  11. S. Zhu, H. Qin, B. Liu and J. Yang, "Design and Optimization of Reconfigurable Data Path for Communication Baseband Signal Processing," International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, pp. 465-4654, 2018.

  12. B. Liu, X. Ruan, M. Xia, Y. Gong, J. Yang, W. Ge and J. Yang, “An Energy-Efficient Accelerator for Hybrid Bit-width DNNs”, IEEE Symposium Series on Computational Intelligence, pp. 1-8, 2018.

  13. Y. Gong, T. Xu, B. Liu, W. Ge, J. Yang, J. Yang and L. Shi, “Processing LSTM in memory using hybrid network expansion model”, IEEE International Workshop on Signal Processing Systems (SiPS), pp. 1-6, 2017.

  14. J. Xiao, B. Liu, “A data cache optimization approach for coarse grain reconfigurable architecture for multimedia applications”, IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB), pp. 1-4, 2016.

  15. B. Liu, Y. Gong, R. Wang, Y. Liu, “Performance-Conscious Reconfiguration Structure for Large-Scale Coarse-grained Reconfigurable System”, 7th International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, pp. 354-359, 2015.

  16. B. Liu, D. Zhang, W. Ge and Y. Gong, “A Novel Routing Structure of Coarse-Grained Reconfigurable Architecture for Radar Application”, 2015 IEEE 11th International Conference on ASIC (ASICON), pp. 1-4, 2015.



GRANTED专利(第一发明人):

国内发明专利

  1. 一种面向多个粗粒度动态可重构阵列的数据缓存更新系统,ZL201610047593.6,授权2019.03.01

  2. 面向MIMO信道检测系统中粗粒度可重构阵列及路由结构,ZL201610101435.4,授权2018.08.20

  3. 基于可重构系统配置多模式传输的可控缓存实现系统,ZL201610098958.8,授权2018.06.19

  4. 基于大规模粗粒度嵌入式可重构系统及其处理方法,ZL201410241289.6,授权2018.02.02

  5. 一种面向FFTFIR的共享数据缓存结构及管理方法,ZL201510104566.3,授权2018.01.30

  6. 一种面向粗粒度可重构系统的多模式动态可配高速访存接口,ZL201510281857.X,授权2018.01.02

  7. 一种面向雷达应用动态可重构处理阵列扩展的方法,ZL201410311140.0,授权2017.02.15

  8. 一种基于粗粒度动态可重构系统的多模式数据访问装置及办法,ZL201410062769.6,授权2017.02.08

  9. 用于粗粒度动态可重构阵列的多模式数据传输互连器,ZL201410157349.6,授权2016.11.23

  10. 一种低电压工作的SRAM的存储单元电路,ZL201210590336.9,授权2015.12.09

  11. 一种SoC集成的多端口DDR2/3调度器及调度方法,ZL201310062166.1,授权2015.12.02

  12. 支持数据预取与重用的可重构系统,ZL201210584470.8,授权2015.09.16

  13. 一种面向嵌入式应用的软件可控Cache的实现方法,ZL200810156535.2,授权2010.03.24



国际发明专利:

  1. B. Liu, Y. Gong, W. Ge, J. Yang, L. Shi, “Multiplication and accumulation calculation method and calculation circuit suitable for neural network”, PCT/CN2019/072892

  2. B. Liu, Y. Gong, W. Ge, J. Yang, L. Shi, “Multi-bit wide PE array calculation bit width selection method and calculation precision control circuit”, PCT/CN2020/094549

  3. B. Liu, Y. Gong, H. Cai, W. Ge, J. Yang, L. Shi, “A deep neural network accelerator based on mixed precision storage”, PCT/CN2020/09455

  4. B. Liu, Y. Gong, W. Ge, J. Yang, L. Shi, “A dual-phase coefficient adjustable analog multiplication calculation circuit for convolutional neural network”, PCT/CN2020/079253



设计竞赛获奖(指导老师):

  1.  2020绍兴九天杯”首届集成电路产业设计大赛总决赛二等奖;(分组赛第一,全国总决赛第二,此项竞赛东南大学所获最高奖项);

  2.  2020首届中国电子信息行业创新创业大赛总决赛优秀奖;(初赛130个参赛组中排名第二);

  3.  2020全国集成电路创新创业大赛全国总决赛一等奖(学生:朱文涛,邹艳勤,孙煜昊);(当年此项竞赛东南大学所获最高奖项之一);

  4.  2020全国集成电路创新创业大赛华东分赛区决赛三等奖(学生:刘明冲,张轩,丁小灵);

  5.  2020“华为杯”第三届中国研究生创“芯”大赛总决赛二等奖(学生:朱文涛,邹艳勤,孙煜昊);(当年此项竞赛东南大学所获最高奖项之一);

  6.  2020年第二届集成电路EDA设计精英挑战赛三等奖×2(博士生组,学生:龚宇,张轩,丁小灵),(硕士生组,学生:张子龙,杨海川,孙煜昊);

  7.  2019年全国大学生“互联网+”创新大赛优秀指导教师;

  8.  2019年全国大学生“互联网+”创新大赛全国总决赛二等奖(学生:朱文涛,邹艳勤);

  9.  2019年全国集成电路创新创业大赛全国总决赛二等奖(学生:李焱,孙煜昊,朱文涛);(当年此项竞赛东南大学所获最高奖项);

  10.  2019年全国集成电路创新创业大赛华东分赛区决赛二等奖(学生:于华振,范虎,刘波);

  11.  2019年全国集成电路创新创业大赛华东分赛区决赛三等奖(学生:杨晶,向丽苹);

  12.  2018年全国大学生FPGA创新设计邀请赛一等奖(学生:于华振,刘波,范虎);(当年此项竞赛东南大学所获最高奖项之一);

  13.  2018年第十三届中国研究生电子设计竞赛团队二等奖(学生:陈爽,王俊,王伟,姜桂泉,王福安);

  14.  2018年中国研究生创新实践系列大赛“华为杯”全国总决赛二等奖(学生:夏梦雯,范虎,于华振);

  15.  2018全国集成电路创新创业大赛华东分赛区决赛三等奖(学生:于华振,杨晶,郭世晟);

  16.  2017年全国大学生FPGA创新设计邀请赛企业特别奖(学生:于华振,杨晶,刘波);

  17.  2017年第七届全国大学生集成电路设计-应用创新大赛总决赛一等奖(学生:秦海,夏梦雯,郑梦瑶);

  18.  2017全国集成电路创新创业大赛全国总决赛三等奖(学生:朱智洋,陈壮,阮星)。



承担科研项目:

  1. 国家科技重大专项:“面向智能计算的高能效精度可控近似计算单元及控制方法研究”,项目经费:500万元2018~2020;项目负责人。

  2. 企业委托技术研发:“极低功耗智能语音识别技术”,项目经费:30万元2018~2020项目负责人

  3. 国家自然科学基金:“面向雷达信号处理动态可重构处理器中阵列路由结构和数据缓存机制的研究”,2014~2017项目负责人


部分项目成果介绍

东南大学成果推荐,第22期,“极低功耗AI语音(声纹)识别芯片”:

https://mp.weixin.qq.com/s/DNYvGfA4SnrufyGkLLeBVQ