中文信息

个人简介

东南大学电子科学与工程学院副教授，硕士生导师。本硕博毕业于东南大学，主要研究低功耗近阈值电压射频集成电路和射频收发机架构设计等，先后承担国家自然科学基金、863科技攻关和军工项目等科研项目，成功研发433M、Zigbee、BLE、超低功耗GNSS多模多频导航芯片、Sub-1GHz LORA射频收发机等多款短距离无线通信芯片，性能均达到国际先进水平。以第一作者或通信作者在集成电路领域顶级会议ISSCC，集成电路领域顶级期刊Journal of Solid-State Circuits，射频电路顶级会议RFIC，以及IEEE知名期刊 TCAS1及TCAS2等期刊上发表学术论文十余篇，授权国内发明专利二十余项，授权美国专利两项。2018年江苏省科学技术奖一等奖1项。所开发的GNSS双模双频导航SoC芯片，以及多普勒测速测距毫米波雷达芯片于南京市低功耗集成电路研究院为平台进行产业化推广中；所开发的Sub-1G短距离射频无线收发芯片已在南方电网自动抄表网络中实际应用2KK以上规模。

教育经历

工作经历

讲授课程

本科课程《通信电子线路》

研究生课程《模拟CMOS集成电路设计》

教学研究

出版物

研究领域或方向

低功耗射频无线收发机芯片、射频接收机前端及中频链路、频率综合器、模数/数模转换器

研究项目

研究成果

[1] C. Chen*, W. Xiang, Y. Zhao, X. Su, J. Chen and J. Yang, “11.4 A Gm-C RF Quadrature-Current-Generation Technique with 40dB IRR in 0.65V 2mW Multi-Mode CMOS GNSS Receiver”, 2025 IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, 2025, pp. 1-3, doi: 10.1109/ ISSCC49661.2025.10904608.

[2] C. Chen*, D. Huang, Y. Zhao, Y. Jin and J. Yang, “An Ultra-Low-Voltage 2.4-GHz Flicker-Noise-Free RF Receiver Front End Based on Switched-Capacitor Hybrid TIA With 4.5-dB NF and 11.5-dBm OIP3”, in IEEE Journal of Solid-State Circuits (JSSC), vol. 58, no. 7, pp. 1825-1837, July 2023, doi: 10.1109/JSSC.2023.3266268.

[3] C. Chen* and J. Wu, “A 1.2-V Self-Reconfigurable Recursive Mixer with Improved IF Linearity in 130-nm CMOS”, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 64, no. 1, pp. 36-40, Jan. 2017, doi: 10.1109/ TCSII.2016.2551541.

[4] C. Chen*, J. Wu, C. Huang and L. Shi, “A CMOS Switched Load Harmonic Rejection Mixer for DTV Tuner Applications”, in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 60, no. 2, pp. 428-436, Feb. 2013, doi: 10.1109/TCSI.2012.2215695.

[5] C. Chen*, J. Wu, D. Huang and L. Shi, “A Low-Power 2.4-GHz Receiver Front End With a Lateral Current-Reusing Technique”, in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 61, no. 8, pp. 564-568, Aug. 2014, doi: 10.1109/TCSII. 2014.2327344.

[6] Wj.Zhang, C.Chen* et al. “A 2.4GHz 676μW Receiver Front-End with Passive Analog FIR Filtering Embedded in Down-Converter Achieving >60dB Blocker Rejection,” IEEE Radio Frequency Integrated Circuits Symposium 2025 (RFIC), San Francisco, CA, USA, 2025.

[7] Y. Zhao, C. Chen* and J. Yang, “A 0.65 V 4 dB NF 2.4 GHz Sub-Passive RF Down-Converter With Trans-Frequency Current-Reusing Scheme Achieving Low Flicker Noise and High Linearity,” in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 7, pp. 3029-3040, July 2024, doi: 10.1109/ TCSI.2024.3399928.

[8] Y. Zhao, C. Chen* and J. Yang, “A 0.55V 10-Bit 100-MS/s SAR ADC With 3.6-fJ/Conversion-Step in 28nm CMOS for RF Receivers”, in IEEE Transactions on Circuits and Systems II: Express Briefs,, vol. 70, no. 6, pp. 1811-1815, June 2023, doi: 10.1109 /TCSII.2021.3117941.

[9] Chen C*, Wu J H, Wang Z X. “150 mA LDO with self-adjusting frequency compensation scheme”. Electronics letters, 2011, 47(13): 767-768.

[10]Chen C*, Wu J H, “A 0.6V 2.1mW RF Receiver based on Passive Mixing and Master-slave Common-Mode Rejection Technique in 65nm CMOS”. Electronics letters, 2016, 52(5): 335-336.

[11]Longxing Shi, Chao Chen*, Jianhui Wu, et al. “A 1.5-V current mirror double-balanced mixer with 10-dBm IIP3 and 9.5-dB conversion gain”. IEEE Transactions on Circuits and Systems II: Express Briefs , 2012, 59(4): 204-208.

学术兼职

团队介绍

招生情况

毕业生介绍